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MSQA6V1W5T2G, SZMSQA6V1W5T2G
The following is taken from Application Note
AND8308/D ? Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000 ? 4 ? 2 waveform. Since the
IEC61000 ? 4 ? 2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
100
90
80
70
60
50
40
30
20
10
t r
t P
PEAK VALUE I RSM @ 8 m s
PULSE WIDTH (t P ) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 m s
HALF VALUE I RSM /2 @ 20 m s
0
0
20
40
60
80
t, TIME ( m s)
Figure 5. 8 X 20 m s Pulse Waveform
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